Continuing reduction of the minimum features produced by semiconductor processes and reduction in the size of the resulting devices has enabled continued improvements in speed, performance, density, and cost per unit function of integrated circuits and systems. As semiconductor process nodes continue to shrink, critical dimensions (“CD”) of the semiconductor devices have approached and even surpassed the theoretical limits of photolithography equipment. At the semiconductor process nodes now being developed, the CD spacing desired is less than the spacing that can be resolved using optical masks and photolithography equipment.
An approach used to achieve the finer resolutions now required is to use double patterning. For example, a “half pitch” line spacing (half of the minimum photolithographic pitch for a given numerical aperture (“NA”) for the photolithography system) can be achieved by using sidewall aligned spacers by forming dummy lines, for example at the minimum available pitch from the photolithographic system, then forming sidewalls on the dummy lines, removing the dummy lines by a selective removal that leaves the sidewalls, and then using the sidewalls as etch patterning masks, transferring the sidewall pattern to underlying layers using selective etch processes. In this manner, a line spacing that is approximately half the minimum pitch can be achieved.
Very fine lines are increasingly used to form structures in semiconductor devices. Recent advances in transistor structures include the use of “FinFET” transistors. In a FinFET, a layer of semiconductor material or a substrate is patterned to form a “fin” shape, which is a thin vertical protrusion extending above the remaining material. A gate dielectric strip is disposed over the sidewalls and sometimes over the top of the fin. A gate conductor is then formed conformally over the gate dielectric. In this manner the gate width of an MOSFET device, for example, may be greatly increased while the silicon area needed for that device is not proportionally increased, due to the use of the area of the vertical fin sidewalls to extend the gate width. Higher performance MOSFET devices may be thus achieved at lower process node sizes, without an undesirable increase in the silicon area needed for each device. The transistor performance can be further increased by using a common gate dielectric and conductor over several fins, further increasing the gate width.
In order to form the fine structures needed at current and future advanced semiconductor processing nodes, such as at 32 nanometer, 28 nanometer, or 22 nanometer semiconductor process nodes and beyond, double patterning will likely be used. Current process approaches to double patterning of fine lines at the “half-pitch” (lines patterned at half of the pitch available from the photolithographic patterning process) exhibit unacceptable uniformity problems related to mask loading and etch bias effects. The outer lines formed in a plurality of lines using the conventional approaches may exhibit a different width than the inner lines formed in a plurality of parallel lines, due to etch bias problems. Isolated lines may also exhibit etch bias non-uniformity. These characteristics make it difficult or impractical to provide the uniform line widths and uniform line spacing required for forming advanced devices, for example, for providing fins for finFET transistors.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.